1. Field of the Invention
The present invention relates in general to an electrostatic discharge protection device. In particular, the present invention relates to an electrostatic discharge protection device immune to latch-up during normal operation.
2. Description of the Related Art
Electrostatic discharge (ESD) is a common phenomenon during the handling of semiconductor integrated circuit (IC) devices. Electrostatic charges may accumulate and cause potentially destructive effects on an IC device. ESD stress can typically occur during a testing phase of IC fabrication, during installation of the IC onto a circuit board, and during use of equipment into which the IC has been installed. Damage to a signal IC due to poor ESD protection in an electronic device can partially or completely disrupt its operation.
FIG. 1 shows a section view of a conventional floating well silicon-controlled rectifier (FW-SCR) formed in a substrate. Conventional floating well silicon-controlled rectifiers (FW-SCR) are usually located on a P-type silicon substrate 10. The P-type substrate 10 comprises an N-type well 11. A P-type doped region 12 is then formed in the N-type well 11. Next, an N-type doped region 14 and P-type doped region 15 are formed in the P-type substrate 10. The P-type doped region 12 is connected to a pad 1 connecting to an internal circuit 2. In addition, the N-type doped region 14 and the P-type doped region 15 are connected to a voltage level Vss. The voltage level Vss is usually ground when the device operates in normal mode.
Therefore, the P-type doped region 12, the N-type well 11, and the P-type silicon substrate 10 serve as the emitter, base, and collector, respectively, of a PNP bipolar junction transistor 20. The N-type well 11, the P-type silicon substrate 10, and the N-type doped region 14 serve as the collector, base, emitter, respectively, of an NPN bipolar junction transistor 21. FIG. 2 shows the equivalent circuit diagram of the protection circuit shown in FIG. 1, and the resistor 22 represents the spreading resistance between the N-type doped region 14 and the P-type silicon substrate 10.
During normal operation, however, latch-up may be abnormally induced by the holes in the substrate during positive triggering, and result in disorder or even error if noise interferes with the integrated circuit.
The object of the present invention is to provide an electrostatic discharge protection device, which adds a first-type deep well to the conventional electrostatic discharge protection device. The first-type deep well is formed between the second-type substrate and a second-type well connected to a predetermined voltage level, and adjoins to the first-type wells, which surround the second-type well. Therefore, the first-type deep well and the first-type wells around the second-type well besiege the second-type well completely, apart from the second-type well and the substrate. Moreover, the first-type well is provided a predetermined voltage to avoid noise or interference current entering the second-type well and causing latch-up.
Moreover, according the present invention, the types of silicon-controlled rectifier are not only floating well, but also low-voltage (LVTSCR), or lateral (LSCR).
To achieve the above-mentioned object, the present invention provides an electrostatic discharge protection device, which comprises the following elements. A first-type substrate is coupled to the second voltage level. A first second-type well is formed on the first-type substrate and coupled to the first voltage level. A second second-type well is formed on the first-type substrate and coupled to the first voltage level. A first-type well is formed between the first second-type well and the second second-type well. A third second-type well is formed between the first-type substrate and the first-type well, and coupled to the first second-type well and the second second-type well. A first-type doped region is formed on the first second-type well and coupled to the pad, and a second-type doped region is formed on the first-type well and coupled to the second voltage level.